An Application-Specific Integrated Circuit (ASIC) is an integrated circuit designed to implement a particular function, and generally no other function. The logic functions of the ASIC are first designed on “paper,” possibly in a symbolic manner, and the paper design is then used to design the functions of the integrated circuit. The transfer from the paper design to the actual product may require implementation of various circuits, which in combination make up a single logic element. The actual fabrication may involve masking, deposition of semiconductor materials onto a substrate, etching, deposition of metal layers onto the substrate, and much more.
For example, FIG. 1D is a simplified diagram in block and schematic form illustrating a traditional structured ASIC constructed with a customized interconnect matrix. Logic elements 31 may be interconnected internally to the logic element block and externally to the logic element block via a masked metal interconnect matrix 32. In its simplest form, interconnect matrix 32 may comprise a single layer of horizontal metal interconnect and a single layer of vertical metal interconnect. At the time of masking, these horizontal and vertical metal interconnects may be selectively joined by forming conductive vias 33 at predetermined overlapping points to form an ASIC implementing a particular function. As no vias are formed where there are no desired connections, ASICs of the prior art do not require initialization, but are configured at the time of manufacture and may not be modified in the field. As a result, the use of ASICs is typically only economically justified when the design and nonrecurring cost of fabrication of the integrated circuit can be amortized over a large number of units.
A Field-Programmable Gate Array (FPGA) is a logic network that can be programmed into the desired device after its manufacture. The gate arrays consist of or include elemental logic gates or logic blocks, the input and output ports of which are interconnected by switches. The elemental logic elements may include gates, lookup tables, Random Access Memories (RAMs), and the like. The interconnection switches may be in the form of reprogrammable cells, or they may be one-use fuse-like elements. The logic network assembled by the use of fuse-like switch elements are permanently set in the original programmed form, while those using reconfigurable elements (typically SRAM) can be reprogrammed to various different logic networks. Thus, a “standard” FPGA can be programmed, in many cases, to perform any of a large number of functions. In this way, a properly programmed FPGA may be configured to perform the same functions as any one of a plurality of ASICs. Thus, while FPGAs may be initially more expensive than ASICs, their nonrecurring development costs and re-configurability may provide an economic benefit.
As mentioned, FPGAs require after-manufacture specialized programming in order to convert the array for the specialized use. This programming sets the programmable interconnection fuses, switches or switch cells to the desired states to implement the desired function. The switch cells may be viewed as being non-volatile, as in the case of a fused-based FPGA, or as being volatile in a manner similar to random-access memory (RAM) cells, in that they retain a set switch state so long as power is applied, and lose the set state when power is removed. That means that the volatile FPGA must be re-programmed in some manner after a loss of power. This reprogramming may be performed at start-up, using some form of nonvolatile stored memorized information relating to the desired switch cell states. Such memorized information may come from a remote computer with a hard drive preprogrammed with the desired switch states, or from a nonvolatile memory such as a flash memory similarly preprogrammed.
FIG. 1A is a simplified diagram in block and schematic form illustrating how specific functional logic blocks of a FPGA may be constructed using an array of standard multiplexers (MUXs or MPXs) such as two or multi-input multiplexers. Arrays of two-input multiplexers, some of which are illustrated in FIG. 1A as 1A11 and 1A12 are interconnected by a North-South interconnection matrix 1A2 and an East-West interconnection matrix 1A3. A detail of the contents of simplified two-input multiplexer array 1A12 is shown as 1A4, with three two-input multiplexers 1A41, 1A42, and 1A43 in a first stage and one two-input multiplexer 1A44 in the second stage, thus providing a nine input and one output logic function. As an example, this multiplexer array is shown to be programmed to give the logic function y=(a & b)|c, to yield the logic gate function equivalent shown in 1A5.
FIG. 1B is a simplified diagram in block and schematic form illustrating how specific functional logic blocks of a FPGA may alternatively be constructed using an array of standard Look-Up Tables, or LUTs. Arrays of Look-Up Tables, some of which are designated 1B11 and 1B12, are interconnected by a North-South interconnection matrix 1B2 and an East-West interconnection matrix 1B3, much as in FIG. 1A. A simplified detail of the contents of three-input one-output LUT 1B12 is shown as 1B4. The LUT 1B12 details as shown in 1B4 include eight rows of table entry required to implement the desired logic function. As an example, this LUT is shown to be programmed to give the logic function y=(a & b)|c, to yield the logic gate function equivalent shown in 1B5 (for illustrative purposes, this is the same logic function implemented in FIG. 1A).
FIG. 1C is a simplified diagram in block and schematic form illustrating how MUX-Based or LUT-Based logic elements 1C1 of a FPGA may be interconnected to the North-South interconnect matrix or bus 1C2 and the East-West interconnect matrix or bus 1C3. In FIG. 1C, the interconnections between the logic elements 1C1 and the interconnect matrices is accomplished by means of a plurality of CMOS transistor switches, one of which is designated 1C4. Each CMOS transistor switch 1C4 is switched on or off by a static random access memory SRAM memory cell 105. Similar SRAM bits 1C4 with transistor switches 105 are used inside logic elements 1C1 to configure (i.e. program) the functionality of the logic elements. For an SRAM-Based FPGA, the SRAM cells are initially in an unknown state at power-up, and are then, at power-up initialization time, programmed to the proper logic one or zero state via an external non-volatile (typically FLASH) memory source or from an external host processor 106 which provides a bit stream 1C7. Thus the functionality, or characterization, of the FPGA may be modified in the field by loading a different initialization bit stream.
More recently, the functions available on FPGAs have become more complex. That is to say, the elemental blocks available for programmable interconnection have tended to become more complex. For example, in addition to providing simple gates, some FPGAs may provide embedded adders, multipliers, memories, and microprocessors and related peripherals, which are capable of being programmably-interconnected by the programmable switches of the array. This complexity allows FPGAs to be used in various functions such as digital radio, radar signal processing, and in massively parallel applications.
The ASIC can generally be expected to use less power, and to be faster and less bulky than a corresponding-function programmed FPGA. The design and manufacture of ASICs may be difficult and time-consuming due to the process and manufacturing steps involved. The FPGA, on the other hand, allows for easy experimentation to optimize performance, and is cheaper for quantities less than some threshold. The FPGA requires a separate programming step after manufacturing, and this step must be customized to the desired application. Due to their various different advantages and disadvantages, ASICs and FPGAs are both in use.
Accordingly, it would be desirable to have a device that has all the advantages of a FPGA and an ASIC, with none of the disadvantages of either.